Znaleziono ~2 oferty w 0.155s, strona 1 z 1
Aplikuj
-

ASIC Verification Engineer

@GS Services UVM ASIC SystemVerilog FPGA IP block verification multi-clock domains HLS C Emulation
Aplikuj
13 300 - 18 300 zł

RTL Validation Engineer

@EndySoft RTL SystemVerilog UVM Perl Python